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Low Input, MHz Operation, High Efficiency Synchronous Buck
POWER MANAGEMENT Description
The SC4608 is a voltage mode step down (buck) regulator controller that provides accurate high efficiency power conversion from an input supply range of 2.7V to 5.5V. A high level of integration reduces external component count, and makes it suitable for low voltage applications where cost, size and efficiency are critical. The SC4608 is capable of producing an output voltage as low as 0.5V. It's frequency of operation is programmable to 1MHz. The SC4608 drives external, N-channel MOSFETs with a peak gate current of 1A. A non-overlap protection is provided for the gate drive signals to prevent shoot through of the MOSFET pair. The SC4608 features lossless current sensing of the voltage drop across the drain to source resistance of the high side MOSFET during its conduction period. The quiescent supply current in sleep mode is typically lower than 1A. A external soft start is provided to prevent output voltage overshoot during start-up. The SC4608 is an ideal choice for converting 3.3V, 5V or other low input supply voltages. It's available in 16 pin MLP package.
SC4608
Features
Asynchronous start up Programmable switching frequency up to 1MHz BiCMOS voltage mode PWM controller 2.7V to 5.5V input voltage range Output voltage as low as 0.5V +/-1% reference accuracy Sleep mode (Icc = 1A max) Adjustable lossless short circuit current limiting Combination pulse by pulse & hiccup mode current limit High efficiency synchronous switching 1A peak current driver External soft start Power good signal 16-pin MLP Lead-free package. This product is fully WEEE and RoHS compliant
Applications
Distributed power architecture Servers/workstations Local microprocessor core power supplies DSP and I/O power supplies Battery-powered applications Telecommunications equipment Data processing applications
Typical Application Circuit
Vin=3V - 3.6V
C10 R13 1 16 C3 1u 1 2 3 C16 560pF C1 180p C2 2.2n R1 14.3k R2 10k Css 22n 4 5 6 7 D2 220u M11 R6 1 12 11 10 9 8 R8 200 R5 1 C17 1u M2 C13 22u C14 22u
R3
SC4608
PVDD AVDD ISET COMP FSET EN PGOOD SS PHASE DRVL PGND AGND VSENSE BST DRVH 15 13
L1 1.8u C6 330u
Vout= 0.5V / 12A
C5 22u C4 22u C9 4.7n R7 10k
Revision: June 19, 2006
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SC4608
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Analog Supply Voltage (AVDD) Power Supply Voltage (PVDD) PGND Output Drivers (DRVH, DRVL) Currents Continuous P eak Inputs (VSENSE, COMP, FSET, ISET, SS) BST PHASE PHASE Pulse tpulse < 50ns Storage Temperature Range Maximum Junction Temperature Peak IR Reflow Temperature, 10 - 40s ESD Rating (Human Body Model)
Symbol
Maximum 6 AVDD+/- 0.3 0.3 0.25 1.00 -0.3 to AVDD +0.3 PVDD +6 -0.3 to PVDD +0.3 -2 to PVDD +1
Units V V V A A V V V V C C C kV
TSTG TJ TPKG ESD
-65 to +150 +150 260 2
All voltages with respect to AGND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, AVDD = 3.3V, AVDD = PVDD , CT = 270pF, TA = -40C to 85C, TA=TJ
Parameter Overall Supply Voltage Supply C urrent, Sleep Supply C urrent, Operati ng AVDD Turn-on Threshold AVDD Turn-off Hysteresi s Error Amplifier FB Voltage (Internal Reference)
Test C onditions
Min
Typ
Max
U nit
5.5 E N = 0V AVDD = 5.5V TA = -40C to 85C 275 350 0.1 2 1 3.75 2.7 425
V A mA V mV
AVDD = 2.7V to 5.5V, TA = -40C to 85C AVDD = 2.7V to 5.5V, TA = 25C TA = -40C to 85C TA = 25C
0.49 0.493 0.492 0.495
0.5 0.5 0.5 0.5 200 90 8
0.51 V 0.507 0.508 0.505 nA dB MHz
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VSENSE Bi as C urrent Open Loop Gai n (1) Uni ty Gai n Bandwi dth (1)
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VSENSE = 0.5V VCOMP = 0.5 to 2.5V
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SC4608
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, AVDD = 3.3V, AVDD = PVDD , CT = 270pF, TA = -40C to 85C, TA=TJ
Parameter Error Amplifier (Cont.) Slew Rate (1) VOUT High VOUT Low Oscillator Initial Accuracy OSC Line Regulation Temperature Coefficient Minimum Operation Frequency (1) Maximum Operation Frequency (1) Ramp Peak to Valley Ramp Peak Voltage Ramp Valley Voltage Soft Start, Current Limit Programmable Soft Start Time (1) Soft Start Charge Current ISET Bias Current Temperature Coefficient of ISET Current Limit Blank Time (1) Gate Drive DRVH Minimum OFF Time (1) Peak Source (DRVH) Peak Sink (DRVH) Peak Source (DRVL) Peak Sink (DRVL) Output Rise Time Output Fall Time Minimum Non-Overlap (1)
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(1)
Test Conditions
Min
Typ
Max
Unit
2.4 ICOMP = -5.5mA ICOMP = 5.5mA
AVDD - 0.5 AVDD - 0.3
V/s V 0.45
0.3
TA = 25C TA = 25C, AVDD = 2.7V to 5.5V TA = -40C to 85C
525
575 1 0.02
625 2.5
kHz %/V %/C kHz
50 1M 1 1.3 0.3
Hz V V V
C = 22nF TA = 25C TJ = 25C -4 -45
2 -5.25 -50 0.3 130 -6.5 -55
ms A A %/C ns
TA = 25C Vgs = 3.3V, ISOURCE = 100mA Vgs = 3.3V, ISINK = 100mA Vgs = 3.3V, ISOURCE = 100mA Vgs = 3.3V, ISINK = 100mA Vgs = 3.3V, COUT = 4.7nF Vgs = 3.3V, COUT = 4.7nF
160 3.5 3 2.2 2 35 27 40 4 6 5
ns ns ns ns
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SC4608
POWER MANAGEMENT Electrical Characteristics
Unless otherwise specified, AVDD = 3.3V, AVDD = PVDD , CT = 270pF, TA = -40C to 85C, TA=TJ
Parameter Pow er Good PGOOD Voltage Low PGOOD Leakage Current PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Delay Enable High Level Threshold Low Level Threshold EN Input Bias Current
Test Conditions
Min
Typ
Max
Unit
IPGOOD = 1mA, AVDD = 5.5V AVDD = 5.5V 7.5 -14.5
0.15
0.3 1
V A % % ms
11.5 -10.5 14
15.5 -6.5
0.7 * AVDD 0.3 * AVDD
V V nA
V E N = 0V
-10
Note: (1). Guaranteed by design.
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SC4608
POWER MANAGEMENT Pin Configuration
TOP VIEW
Ordering Information
Part Number SC4608MLTRT(2) S C 4608E V B Device(1) MLP-16 Evaluation Board
Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(16 Pin MLP)
Pin Descriptions
Pin # 1 2 Pin Name AVDD ISET Pin Function Power supply voltage for the analog section of the controller. The ISET pin is used to limit current in the high side MOSFET. The SC4608 uses the voltage across the VIN and ISET pins in order to set the current limit. The current limit threshold is set by the value of an external resistor (R3 in the Typical Application Circuit Diagram). Current limiting is performed by comparing the voltage drop across the sense resistor with the voltage drop across the drain to source resistance of the high side MOSFET during the MOSFET's conduction period. The voltage drop across the drain to source resistance of the high side MOSFET is obtained from the VIN and PHASE pin. This is the output of the voltage error amplifier. The voltage at this output is inverted internally and connected to the non-inverting input of the PWM comparator. A lead-lag network from the COMP pin to the VSENSE pin compensates for the two pole LC filter characteristics inherent to voltage mode control. The lead-lag network is required in order to optimize the dynamic performance of the voltage mode control loop. The FSET pin is used to sets the PWM oscillator frequency through an external timing capacitor that is connected from the FSET pin to the GND pin. The SC4608 can be operated in synchronous mode by placing a resistor in series between the timing capacitor and ground. The other terminal of the timing capacitor will remain connected to the FSET pin. The oscillator frequency of the SC4608 is set by FSET when EN is pulled and held above 0.7 * AVDD. Its shutdown mode is invoked if EN is pulled and held below 0.3 * AVDD.
3
COMP
4
FS E T
5
EN
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SC4608
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin # 6 7 Pin Name PGOOD SS Pin Function Power good open drain output. Low when the output is below the power good threshold level. Soft start. A capacitor to ground sets the soft start time. The soft start time is independent of switching frequency and is defined as SS = 0 . 09 * C . Where C is the external capacitor in nF and SS is the soft start time in ms. This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the Buck converter. VSENSE is compared to an internal reference value of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired. For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical Application Circuit Diagram). Analog ground. Power ground. DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The output drivers are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics. The PHASE pin is used to limit current in the high side MOSFET. The SC4608 uses the voltage across the VIN and ISET pin in order to set the current limit. The current limit threshold is set by the value of an external resistor (R3 in the Typical Application Circuit Diagram). Current limiting is performed by comparing the voltage drop across the sense resistor with the voltage drop across the drain to source resistance of the high side MOSFET during the MOSFET's conduction period. The voltage drop across the drain to source resistance of the high side MOSFET is obtained from the VIN and PHASE pin. DRVH drives the gate of the high side (main switch) MOSFET. The output drivers are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics. No connection. This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a sufficient gate-to-source voltage level for driving the gate of the high side MOSFET. Power supply voltage for low side MOSFET. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
8
VSENSE
9 10 11
AGND PGND DRVL
12
PHASE
13
DRVH
14 15
NC BST
16
PVD D Thermal Pad
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SC4608
POWER MANAGEMENT Block Diagram
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SC4608
POWER MANAGEMENT Application Information
Enable The SC4608 is enabled by applying a voltage greater than 2.7 volts to the AVDD pin. The SC4608 is disabled when AVDD falls below 2.35 volts or when sleep mode operation is invoked by clamping the EN pin to a voltage below 0.3*AVDD. 0.1A is the typical current drawn through the AVDD pin during sleep mode. During the sleep mode, the high side and low side MOSFETs are turned off and the internal soft start voltage is held low. Oscillator The FSET pin is used to set the PWM oscillator frequency through an external timing capacitor that is connected from the FSET pin to the GND pin. The resulting ramp waveform ion the FSET pin is a triangle at the PWM frequency with a peak voltage of 1.3V and a valley voltage of 0.3V. 160ns minimum OFF time for the top switch allows the bootstrap capacitor to be charged during each cycle. The capacitor tolerance adds to the accuracy of the oscillator frequency. The approximate operating frequency and soft start time are both determined by the value of the external timing capacitor as shown in Table 1.
External Timing C apacitor Value (pF) 120 270 470 560 Frequency (kH z ) 1000 575 350 295
The maximum frequency of the external clock signal can be higher than the natural switching frequency by about 10%.
FSET External Clock Signal C R 1k D RSYNC 100 CFSET
SC4608 A
56pF
Figure 1 UVLO When the EN pin is not pulled and held below 0.3*AVDD, the voltage on the AVDD pin determines the operation of the SC4608. As AVDD increases during start up, the UVLO block senses AVDD and keeps the high side and low side MOSFETs off and the internal soft start voltage low until AVDD reaches 2.7V. If no faults are present, the SC4608 will initiate a soft start when AVDD exceeds 2.7V. A hysteresis (350mV) in the UVLO comparator provides noise immunity during its start up. Power Good Indicator The PGOOD pin is the open-drain output of the power good comparators. These comparators are incorporated with small amount of hysteresis. A pull-up resistor from the PGOOD pin to the input supply or the output sets the logic high level of the PGOOD signal. The VSENSE low-tohigh trip voltage of the power good comparator is 89% of the final regulation voltage. The power good comparator output becomes valid provided that VO is within about 11% of the programmed output voltage. In shutdown mode the power good output is actively pulled low. The PGOOD signal delay depends on its operating frequency fs, for example, about 14ms@ fs=575kHz and 24ms @ fs=330kHz. Soft Start The soft start function is required for step down controllers to prevent excess inrush current through the DC bus during start up. Generally this can be done by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up the error amp reference. The closed loop creates narrow
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Table 1. Operating Frequency value Based on the Value of the External Timing Capacitor Placed Across the FSET and GND Pins Synchronous mode operation is invoked by using a signal from an external clock. A low value resistor (100 typical) must be inserted in series with the timing capacitor between the timing capacitor and the GND pin. The other terminal of the timing capacitor will remain connected to the FSET pin. The transformed external clock signal is then connected to the junction of the external timing capacitor and the added resistor RSYNC as shown in Figure 1.
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SC4608
POWER MANAGEMENT Application Information (Cont.)
width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. With this, the inrush current from the input side is controlled. The duration of the soft start in the SC4608 is controlled by an external capacitor. SS, the start-up time is defined as: When the converter detects an over current condition (I > IMAX) as shown in Figure 2, the first action the SC4608 takes is to enter the cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases. Then the output voltage is monitored. If the over current and low output voltage (set at 70% of nominal output voltage) occur at the same time, the Hiccup mode operation (Point C to Point D) of the SC4608 is invoked and the internal soft start capacitor is discharged. This is like a typical soft start cycle: Figure 2. Over current protection characteristic of SC4608
SS = 0 . 09 * C
where, C is the value of the external capacitor in nF, and SS is the start-up time in ms. Over Current Protection The SC4608 detects over current conditions by sensing the voltage across the drain-to-source of the high side MOSFET. The SC4608 determines the high side MOSFET current level by sensing the drain-to-source conduction voltage across the high side MOSFET via the Vin (see the Typical Application Circuit on page 1) and PHASE pin during the high side MOSFETs conduction period. This voltage value is then compared internally to a user programmed current limit threshold. Note that user should place Kelvin sensing connections directly from the high side MOSFET source to the PHASE pin. The current limit threshold is programmed by the user based on the RDS(on) of the high side MOSFET and the value of the external set resistor RSET (where RSET is represented by R3 in the applications schematics of this document). The SC4608 uses an internal current source to pull a 50A current from the input voltage to the ISET pin through external resistor RSET. The current limit threshold resistor (RSET) value is calculated using the following equation:
R SET = IMAX R DS( ON) 50A
V O - nom
A
B
0 . 6 VO - nom 7
C
VO
D
IO
IMAX
Power MOSFET Drivers The SC4608 has two drivers which are optimized for driving external power N-Channel MOSFETs. The driver block consists two 1 Amp drivers. DRVH drives the high side N-MOSFET (main switch), and DRVL drives the low side N-MOSFET (synchronous rectifier transistor). The output drivers also have gate drive non-overlap mechanism that provides a dead time between DRVH and DRVL transitions to avoid potential shoot through problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, the SC4608 is capable of driving a converter with up to 12A of output current. As shown in Figure 3, td1 the delay from the , top MOSFET off to the bottom MOSFET on is adaptive by detecting the voltage of the phase node. td2, the delay from the bottom MOSFET off to the top MOSFET on is fixed, is 40ns for the SC4608. This control scheme guarantees avoidance of cross conduction or shoot through
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The RDS(ON) sensing used in the SC4608 has an additional feature that enhances the performance of the over current protection. Because the RDS(ON) has a positive temperature coefficient, the 50A current source has a positive coefficient of about 0.3%/C providing first order correction for current sensing vs temperature. This compensation depends on the high amount of thermal transferring that typically exists between the high side NMOSFET and the SC4608 due to the compact layout of the power supply.
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SC4608
POWER MANAGEMENT Application Information (Cont.)
between the upper and lower MOSFETs and also minimizes the conduction loss in the body diode of the bottom MOSFET for high efficiency applications.
TOP MOSFET Gate Drive BOTTOM MOSFET Gate Drive
must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation is:
IPEAK = IOMAX + Ip -p 2
Phase node
Ground
td1
td2
The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce inductor's copper loss. The core loss can be found in the manufacturer's datasheet. The inductor' copper loss can be estimated as follows:
PCOPPER = I2LRMS R WINDING
Figure 3. Timing Waveforms for Gate Drives and Phase Node Inductor Selection The factors for selecting the inductor include its cost, efficiency, size and EMI. For a typical SC4608 application, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the inductor value will decrease the ripple level of the output voltage while the output transient response will be degraded. Low value inductors offer small size and fast transient responses while they cause large ripple currents, poor efficiencies and more output capacitance to smooth out the large ripple currents. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. A good tradeoff among its size, loss and cost is to set the inductor ripple current to be within 15% to 30% of the maximum output current. The inductor value can be determined according to its operating point and the switching frequency as follows:
L= VOUT ( VIN - VOUT ) VIN fs I IOMAX
Where: ILRMS is the RMS current in the inductor. This current can be calculated as follow is:
ILRMS = IOMAX 1 + 1 I2 3
Output Capacitor Selection Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the SC4608 regulates the inductor current to a new value during a load transient, the output capacitor delivers all the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Surface mount speciality polymer aluminum electrolytic chip capacitors in UE series from Panasonic provide low ESR and reduce the total capacitance required for a fast transient response. POSCAP from Sanyo is a solid electrolytic chip capacitor that has a low ESR and good performance for high frequency with a low profile and high capacitance. Above mentioned capacitors are recommended to use in SC4608 application. Input Capacitor Selection The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction
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Where: fs = switching frequency and I = ratio of the peak to peak inductor current to the maximum output load current. The peak to peak inductor current is:
Ip -p = I * IOMAX
After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core
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SC4608
POWER MANAGEMENT Application Information (Cont.)
mode, the RMS value of the input capacitor can be calculated from:
ICIN(RMS ) = IOMAX VOUT ( VIN - VOUT ) V 2IN
Where: IB = the boost current and VD= discharge ripple voltage. With fs = 300kH, VD=0.3V and IB = 50mA, the required capacitance for the boost capacitor is:
Cboost = IB 1 0.05 1 Dmax = 0.95 = 528nF VD fs 0.3 300k
This current gives the capacitor's power loss as follows:
PCIN = I2 CIN(RMS ) R CIN(ESR )
This capacitor's RMS loss can be a significant part of the total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor's ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by:
CIN = IOMAX D (1 - D) fs ( VI - IOMAX R CIN(ESR ) )
Power MOSFET Selection The SC4608 can drive an N-MOSFET at the high side and an N-MOSFET synchronous rectifier at the low side. The use of the high side N-MOSFET will significantly reduce its conduction loss for high current. For the top MOSFET, its total power loss includes its conduction loss, switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bottom diode, shown as follows:
ITOP _ PEAK VI fs VGATE RG
Where: D = VO/VI , duty ratio and VI = the given input voltage ripple. Because the input capacitor is exposed to the large surge current, attention is needed for the input capacitor. If tantalum capacitors are used at the input side of the converter, one needs to ensure that the RMS and surge ratings are not exceeded. For generic tantalum capacitors, it is wise to derate their voltage ratings at a ratio of 2 to protect these input capacitors. Boost Capacitor Selection The boost capacitor selection is based on its discharge ripple voltage, worst case conduction time and boost current. The worst case conduction time Tw can be estimated as follows:
Tw = 1 Dmax fs
PTOP _ TOTAL = I2 TOP _ RMS R TOP _ ON +
(Q GD + Q GS 2 ) + Q GT VGATE fs + (Q OSS + Q rr ) VI fs
Where: RG = gate drive resistor, QGD = the gate to drain charge of the top MOSFET, QGS2 = the gate to source charge of the top MOSFET, QGT = the total gate charge of the top MOSFET, QOSS = the output charge of the top MOSFET and Qrr = the reverse recovery charge of the bottom diode. For the top MOSFET, it experiences high current and high voltage overlap during each on/off transition. But for the bottom MOSFET, its switching voltage is the bottom diode's forward drop during its on/off transition. So the switching loss for the bottom MOSFET is negligible. Its total power loss can be determined by:
PBOT _ TOTAL = I2 BOT _ RMS R BOT _ ON + Q GB VGATE fs + ID _ AVG VF
Where: fs = the switching frequency and Dmax = maximum duty ratio. The required minimum capacitance for boost capacitor will be:
Cboost =
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Where: QGB = the total gate charge of the bottom MOSFET and VF = the forward voltage drop of the bottom diode.
IB TW VD
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SC4608
POWER MANAGEMENT Application Information (Cont.)
For a low voltage and high output current application such as the 3.3V/1.5V@12A case, the conduction loss is often dominant and selecting low RDS(ON) MOSFETs will noticeably improve the efficiency of the converter even though they give higher switching losses.
C1 C2 L1 PHASE
V out
COMP VSENSE
C9 C4 R7 R
The gate charge loss portion of the top/bottom MOSFET's total power loss is derived from the SC4608. This gate charge loss is based on certain operating conditions (fs, VGATE, and IO). The thermal estimations have to be done for both MOSFETs to make sure that their junction temperatures do not exceed their thermal ratings according to their total power losses PTOTAL, ambient temperature TA and their thermal resistance RJA as follows:
TJ(max) < TA + PTOTAL R JA
R1
S C 4608
R8
R9
Figure 4. Compensation network provides 3 poles and 2 zeros. For voltage mode step down applications as shown in Figure 4, the power stage transfer function is:
1+ G VD (s) = VI s 1 RC C4
Loop Compensation Design For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. The SC4608 has an internal error amplifier and requires the compensation network to connect among the COMP pin and VSENSE pin, GND, and the output as shown in Figure 4. The compensation network includes C1, C2, R1, R7, R8 and C9. R9 is used to program the output voltage according to:
VO = 0.5 (1 + R7 ) R9
1+ s
L1 + s 2L 1C 4 R
Where: R = load resistance and RC = C4's ESR. The compensation network will have the characteristic as follows:
s s 1+ Z1 Z 2 GCOMP (s) = I s s s 1+ 1+ P1 P 2 1+
Where
I = 1 R 7 ( C1 + C 2 ) 1 R1 C 2
Z1 = Z 2 =
1 (R 7 + R 8 ) C 9 C1 + C 2 R 1 C1 C 2
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P1 =
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SC4608
POWER MANAGEMENT Application Information (Cont.)
P 2 = 1 R 8 C9
Layout Guidelines In order to achieve optimal electrical, thermal and noise performance for high frequency converters, special attention must be paid to the PCB layouts. The goal of layout optimization is to identify the high di/dt loops and minimize them. The following guideline should be used to ensure proper functions of the converters. 1. A ground plane is recommended to minimize noises and copper losses, and maximize heat dissipation. 2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if possible. 3. The AVDD bypass capacitor should be placed next to the AVDD and AGND pins. 4. The trace connecting the feedback resistors to the output should be short, direct and far away from the noise sources such as switching node and switching components. 5. Minimize the traces between DRVH/DRVL and the gates of the MOSFETs to reduce their impedance to drive the MOSFETs. 6. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. 7. ISET and PHASE connections to the top MOSFET for current sensing must use Kelvin connections. 8. Maximize the trace width of the loop connecting the inductor, bottom MOSFET and the output capacitors. 9. Connect the ground of the feedback divider and the compensation components directly to the AGND pin of the SC4608 by using a separate ground trace. Then connect this pin to the ground of the output capacitor as close as possible
After the compensation, the converter will have the following loop gain:
s 1+ 1 s s 1 I VI 1 + 1+ RC C 4 Z1 Z 2 VM T(s) = GPWM GCOMP (s) G VD (s) = s s L s 1+ 1+ 1 + s 1 + s 2L1C P1 P 2 R
Where: GPWM = PWM gain VM = 1.0V, ramp peak to valley voltage of SC4608 The design guidelines for the SC4608 applications are as following: 1. Set the loop gain crossover corner frequency C for given switching corner frequency S = 2fs, 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select Z1 and Z2 such that they are placed near O to damp the peaking and the loop gain has a -20dB/dec rate to go across the 0dB line for obtaining a wide bandwidth. 4. Cancel the zero from C4's ESR by a compensator pole P1 (P1 = ESR = 1/( RCC4)). 5. Place a high frequency compensator pole p2 (p2 = fs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at C. The compensated loop gain will be as given in Figure 5:
T Z1 o Z2 Gvd 0dB c p1 p2 Power stage ESR Loop gain -
Figure 5. Asymptotic diagrams of power stage and its loop gain
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SC4608
POWER MANAGEMENT Application Information (Cont.)
Design Example 1. 3V to1.5V @10A application with SC4608
Vin=3V - 5.5V
C10 R13 1 16 C3 1u 1 2 3 C16 470pF C1 1.8n C2 2.2n R1 14.3k R2 10k Css 22n 4 5 6 7 D2 220u M11 R6 0 12 11 10 9 8 R8 107 R5 0 C17 1u M2 C13 22u C14 22u
R3
SC4608
PVDD AVDD ISET COMP FSET EN PGOOD SS PHASE DRVL PGND AGND VSENSE BST DRVH 15 13
L1 2.3u C7 330u
Vout=1.5V/ 10A
C5 22u C4 22u C9 8.2n R7 5.76k
R9 2.87k
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SC4608
POWER MANAGEMENT Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Qty 1 1 1 4 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 C1 C2 C 17 C 4,C 5, C 13, C 14 C7 C9 C 16 D2 L1 M1, M2 R1 R3 R7 R8 R9 R13 C3 C 10 C ss U1 R2 R eference 1.8nF 2.2nF 1uF 22uF, 1206 330uF, 2870 8.2nF 470pF MBR0520LT1 2.3uH Powerpack, SO-8 14.3K 1.33K 5.76K 107 2.87K 1 1uF, 0805 220uF, 2870 22nF S C 4608 10k Semtech P/N: SC 4608IMLTRT Sanyo P/N: 6TPB220ML ON Semi P/N: MBR0520LT1 C ooper Electroni c P/N: HC 1-2R3 Vi shay P/N: Si 7882D P TD K P/N: C 3225X5R0J226M Sanyo P/N: 6TPB330ML Value Part N o./Manufacturer
Unless speci fi ed, all resi stors have 1% preci si on wi th 0603 package. Resi stors are +/-1% and all capaci tors are +/-20%
2006 Semtech Corp.
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SC4608
POWER MANAGEMENT PCB Layout
COMPONENT SIDE (TOP)
COMPONENT SIDE (BOTTOM)
2006 Semtech Corp.
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SC4608
POWER MANAGEMENT PCB Layout (Cont.)
(TOP) (BOTTOM)
(INTER LAYER 1)
(INTER LAYER 2)
2006 Semtech Corp.
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SC4608
POWER MANAGEMENT Outline Drawing - MLP-16
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
B
A A1 A2 b D D1 E E1 e L N aaa bbb .040 .031 .002 .000 (.008) .010 .012 .014 .153 .157 .161 .100 .106 .110 .153 .157 .161 .100 .106 .110 .026 BSC .012 .016 .020 16 .003 .004 0.80 1.00 0.00 0.05 (0.20) 0.25 0.30 0.35 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.65 BSC 0.30 0.40 0.50 16 0.08 0.10
A
D
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1
D1
C e/2
LxN E/2
SEATING PLANE
E1
2 1 N e D/2 bxN bbb CAB
NOTES: 1. 2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2006 Semtech Corp.
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SC4608
POWER MANAGEMENT Land Pattern - MLP-16
K
DIM
2x (C) H 2x G 2x Z C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.156) .122 .106 .106 .026 .016 .033 .189 (3.95) 3.10 2.70 2.70 0.65 0.40 0.85 4.80
Y X P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp.
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